1. Field of the Invention
The present invention relates to a solid-state imaging device represented by a CMOS image sensor and a camera system.
2. Description of the Related Art
For manufacturing of the CMOS image sensor, a manufacturing process same as that for a general CMOS integrated circuit can be used. The CMOS image sensor can be driven by a single power supply. In the CMOS image sensor, an analog circuit and a logic circuit manufactured by using a CMOS process can be mixed in the same chip.
Therefore, the CMOS image sensor has plural significant advantages such as an advantage that the number of peripheral ICs can be reduced.
As an output of an output circuit of a CCD, a one-channel (ch) output by an FD amplifier having a floating diffusion layer (FD) is mainly used.
On the other hand, the CMOS image sensor has an FD amplifier for each of pixels. As an output of the CMOS image sensor, a column-parallel output for selecting certain one row in a pixel array and simultaneously reading out pixels in the row in column direction is mainly used.
This is because it is difficult to obtain a sufficient driving ability with the FD amplifier arranged in the pixel and, therefore, it is necessary to reduce a data rate and parallel processing is advantageous.
Various circuits are proposed as an image signal readout (output) circuit of the column-parallel output CMOS image sensor.
One of the most advanced forms of the circuits is a circuit of a type that includes an analog-digital converter (hereinafter abbreviated as ADC) for each of columns and extracts a pixel signal as a digital signal.
CMOS image sensors mounted with such column-parallel ADCs are disclosed in, for example, W. Yang et al., “An Integrated 800×600 CMOS Image System,” ISSCC Digest of Technical Papers, pp. 304-305, February, 1999 and JP-A-2005-278135.
FIG. 1 is a block diagram of a configuration example of a solid-state imaging device (a CMOS image sensor) mounted with column-parallel ADCs.
A solid-state imaging device 1 includes, as shown in FIG. 1, a pixel unit 2, a vertical scanning circuit 3, a horizontal transfer scanning circuit 4, and a column processing circuit group 5 including an ADC group.
The solid-state imaging device 1 further includes a digital-analog converter (hereinafter abbreviated as DAC) 6 and an amplifier circuit (S/A) 7.
In the pixel unit 2, unit pixels 21 including photodiodes (photoelectric conversion elements) and intra-pixel amplifiers are arranged in a matrix shape.
In the column processing circuit group 5, column processing circuits 51 are arrayed in plural columns to form ADCs in the respective columns.
The column processing circuits (ADCs) 51 include comparators 51-1 that compare a reference signal RAMP (Vslop) as a ramp waveform (RAMP) obtained by stepwise changing a reference signal generated by the DAC 6 and analog signals obtained, for respective row lines, from the pixels through vertical signal lines.
The column processing circuits 51 further include counter latches (memories) 51-2 that count comparison times of the comparators 51-1 and store results of the count.
The column processing circuits 51 have an n-bit digital signal converting function and are arranged in respective vertical signal lines (column lines) 8-1 to 8-n. Consequently, column-parallel ADC blocks are formed.
Outputs of the memories 51-2 are connected to a horizontal transfer line 9 having, for example, k-bit width. k amplifiers circuits 7 corresponding to the horizontal transfer line 9 are arranged.
FIG. 2 is a timing chart of the circuits shown in FIG. 1.
In the column processing circuits (ADCs) 51, analog signals (potential Vsl) read out to the vertical signal lines 8 are compared with the reference signal RAMP (Vslop), which changes stepwise, by the comparators 5-1 arranged in the respective columns.
The count is performed by the counter latches 51-2 until levels of the analog potentials Vsl and the reference signal RAMP (Vslop) cross and outputs of the comparators 51-1 are inverted. The potentials (the analog signals) Vsl of the vertical signal lines 8 are converted into digital signals (AD-converted).
The AD conversion is performed twice in one readout.
In the first AD conversion, a reset level (P phase) of the unit pixels 21 is read out to the vertical signal lines (8-1 to 8-n) and the AD conversion is executed.
The reset level P phase includes fluctuation in each of the pixels.
In the second AD conversion, signals photoelectrically converted by the unit pixels 21 are read out to the vertical signal lines 8 (8-1 to 8-n) (D phase) and the AD conversion is executed.
The D phase also includes fluctuation in each of the pixels. Therefore, correlated double sampling (CDS) can be realized by executing (a D phase level-a P phase level).
The signals converted into digital signals are recorded in the counter latches 51-2, readout to the amplifier circuits 7 via the horizontal transfer line 9 in order by the horizontal (column) transfer scanning circuit 4, and finally output.
In this way, column-parallel output processing is performed.
Count processing of the counter latches 51-2 during the P phase is referred to as primary sampling. Count processing of the counter latches 51-2 during the D phase is referred to as secondary sampling.